arbitration logic

英 [ˌɑːbɪˈtreɪʃn ˈlɒdʒɪk]

美 [ˌɑːrbɪˈtreɪʃn ˈlɑːdʒɪk]

网络仲裁逻辑; 仲裁逻辑机制; 仲裁电路; 仲裁机制

The improved model of input buffer presented is to insert a quasi random memory between input queue and arbitration logic at ATM switching unit.
改进的输入缓冲方案是在ATM交换单元的输入队列和仲裁逻辑之间加入一个准随机存储器。
Practical application shows that the bus arbitration logic mentioned above is characteristic of low arbitration overhead, fine scalability and higher reliability.
实际运行表明：该仲裁逻辑电路具有仲裁开销小、扩缩性好、可靠性高等特点；
The construction principle, arbitration logic control of dual-port RAM and related usage characteristics are introduced.
介绍了双口RAM的结构原理、仲裁逻辑控制及相应的使用特点；
Focuses are put on band-width design, techniques for multi-clock design, memory arbitration logic, and implement of color expansion.
另外讨论了实现设计中总线宽度，多时钟设计，显示存储器仲裁逻辑，颜色扩展的实现等关键问题。
The two modules are completely independent and symmetrical, either one has the independent arbitration and logic.
这两个部分是完全独立和对称的，每一部分有独立的仲裁和判断逻辑。